• Support Bare, Sv39, and Sv48 modes, as defined in the RISC-V Priv. Spec
• Optional parity checking

• Support 16 regions with a minimum region size of 4096 bytes
• Fixed PMA

• RISC-V standard Hardware performance monitor support
• Help micro-architecture level analysis and performance tuning

• PLIC Interrupts: 1,024 configurable interrupt signals, which can be connected to devices outside the core subsystem
• PLIC supports 8 priority levels
• CLINT: support up to 32 Configurable interrupt targets or harts

• Standard RISC-V debug support
• Standard RISC-V trace interface support

• L1 instruction cache
- Default 32 KB, 4-way associate
- Optional parity checking
• L1 data cache
- Default 32 KB, 4-way set-associate
- Out-of-order processing, non-blocking cache design
- Optional ECC
• L2 cache
- Core cluster level shared between cores
- Configurable capacity size
- Optional ECC

• Core level Wait For Interrupt mechanism
• Core land cluster level clock gating
• Core and cluster level low-power states (Power ON/OFF/Retention)
• Cluster-level frequency scaling

• Bare Metal SDK
- Compiler and toolchains, including two packages based on GCC and LLVM frameworks
- GDB debugger and pre-built OpenOCD
- Sample projects
• Linux SDK
- Yocto-based environment
- Kernel 6.1
- OpenSBI
- Host development tools
• StarFive StarStudio
- Provide stand-alone and pre-built IDE for customers