• Decoupled structure of instruction fetch and branch prediction
• Fetch width: 16 byte per cycle
• RAS predictor for return instruction
• IJTP predictor for indirect-jump instruction
• TAGE style predictor for conditional branch instruction

• 5-Way Decode/Rename/Commit
• ROB Entries: 160
• Integer physical register file entries: 160
• Floating-point physical register file entries: 160

• 2 independent full ALU units
• 1 full ALU unit reusing MDU resources
• 1 independent branch execution unit

• Support the IEEE 754--2008 floating-point standard for 32-bit single-precision and 64-bit double-precision arithmetic

• Support bare, Sv39, and Sv48 modes, as defined in the RISC-V Priv.Spec
• Support 32-entry fully-associative ITLB
• Support 48-entry DTLB
• Support 1280-entry 5-way set associative STLB

• L1 instruction cache
- Configurable set-associative instruction cache
- Default 64 KB, 4-way set associate
- Support data prefetch
- Optional parity check
• L1 data cache
- Default 64 KB, 4-way set associate
- Two load/store pipes
- Support cache writing policy: writeback
- Out-of-order processing, nonblocking cache design
- Support custom CMO instructions
- Optional ECC
• L2 cache
- Default 2 MB, 8-way set associate
- Support L2 cache prefetch
- MESI coherency
- Support cache writing policy: writeback
- Core cluster level shared between cores
- Optional ECC

• Support 64 regions with a minimum region size of 4096 bytes
• Support fixed PMA

• RISC-V standard Hardware performance monitor support
• Help micro-architecture level analysis and performance tuning

• Core level Wait For Interrupt mechanism
• Core land cluster level clock gating
• Core and cluster level low-power states (Power ON/OFF/Retention)
• Cluster-level frequency scaling

• PLIC Interrupts: 1,024 configurable interrupt signals, which can be connected to devices outside the core subsystem.
• PLIC priority levels: PLIC supports 8 priority levels

• Up to 32 Configurable interrupt targets or harts

• Standard RISC-V debug support

• Bare Metal SDK
- Compiler and toolchains, including two packages based on GCC and LLVM frameworks
- GDB debugger and pre-built OpenOCD
- FreeRTOS
- sample projects
• Linux SDK
- Yocto-based environment
- Kernel 6.6
- Host development tools
- OpenSBI
- KVM
- Xvisor
• StarFive StarStudio
- Provide stand-alone and pre-built IDE for customers

• Standard RISC-V trace interface support