• Support all main RISC-V extension (RV64GCBH)

• Support interrupt, debug, trace that compliant with RISC-V specification

• Support high-performance, highly scalable, and cache-coherent NoC connecting CPU cores with system components, achieving high speed, low power consumption, and low latency, with support for up to 256 cores in an SoC.

• This solution can easily integrate the AMBA interface with existing IPs

• Security solution: RISC-V Trusted Execution Environment, RISC-V secure boot, and secure debugging

• A CPU cluster supports advanced power management, with each core and each cluster supporting dynamic frequency scaling (DFS), power states (ON/OFF/Retention), temperature/voltage sensors, and performance monitoring.

• Achieves efficient and high-performance cores through power optimization.